This invention relates generally to a method for inspecting a bare highly polished planar surface of a dielectric or semiconductor material for contaminants thereon.
In manufacturing semiconductor devices, multiple identical microcircuits are formed on bare highly polished planar semiconductor (silicon) wafers using a variety of sophisticated automated equipment (tools, machines). Critically essential to this manufacturing process is a requirement that the wafers are free of contaminants on or at their surface (e.g.: particles, scratches, etc.). To this end, the semiconductor manufacturing equipment is specifically designed, tested, and assembled in clean rooms prior to shipment to minimize all sources that could contaminate a wafer surface during use of the equipment. Additionally, upon arrival at the semiconductor fabrication facility the equipment is installed in large clean room areas that are also stringently controlled to minimize the possibility of wafer contamination, especially from airborne particles.
Many microcircuit chips are produced per wafer. Particle deposition on a wafer is a major cause of non-functional chips. A particle on a wafer surface can cause (1) an electrical “open” or “shorted” circuit, depending on its location relative to the electrical conductors or (2) damage to the chip as a result of chemical reactions surrounding the particle. The reduction of particle generating materials and sources in the manufacturing equipment and fabrication facility reduces wafer surface contamination, thereby improving the yield per wafer. The yield or percentage of “good” chips is the ratio of functional chips at the end of manufacturing to the total number of potential chips that could be produced from a wafer. The chip or die yield can range from 40% to 90%, depending on the maturity of the manufacturing process. As the microcircuit line widths formed on a wafer become smaller, the critical or “killer” defect size also decreases. The “killer” defect size is currently considered to be 1/10th the size of the smallest line width on a microcircuit.
At key points and times during the microcircuit fabrication process, test wafers are cycled through a manufacturing tool and inspected to determine the average number of particles added to a wafer as it passes through the manufacturing tool. The inspection results are expressed in particles per wafer pass (PWP) or in particles/cm2/pass. The test wafers are typically bare silicon and referred to as monitor wafers. PWP testing is well known in the semiconductor industry and is defined by SEMI (Semiconductor Equipment and Material Industry) standards.
It is necessary to reliably determine the size of contaminants so that pass/fail criterion can be applied to the PWP test results. For example, a criterion could be that the manufacturing tool is clean if ≦2 particles of size ≦0.10 micron were added to a test wafer. In the event the criterion is exceeded, the manufacturing tool is taken out of production. Many additional runs of test wafers through the manufacturing tool are usually required to determine the source of the contamination.
If contaminants are added to a test wafer during a PWP test, it is also important to determine their material and other characteristics to more quickly identify and eliminate their source. Typically, the test wafer is transferred to an off-production-line Scanning Electron Microscope-Energy Dispersive X-ray (SEM-EDX) for material analysis. Because of the high magnification of this instrument, searching for sub-micron contaminants can be time consuming. Therefore, the contaminant coordinates, relative to a known datum on the wafer (e.g.: the wafer notch), must be accurately mapped by the wafer inspection tool.
Though many apparatus and methods for locating/sizing contaminants on wafers have been revealed in the prior art (e.g.: U.S. Pat. No. 6,215,551 [Nikoonahad, et al.] and U.S. Pat. No. 6,122,047 [Stover, et al.], etc.) it is thought that drawbacks exist. Chief among the drawbacks is the fact that existing wafer scanning tools, based on the prior art, are located and used off-the-process line due primarily to size, weight, and lack of portability (sensitivity to movement). This requires that the PWP test wafer be (1) transported to the wafer scanning tool for a pre-scan, (2) transported to a manufacturing tool, (3) run through the manufacturing tool/robot, (4) transported back to the wafer scanning tool for a post-scan, and possibly (5) transported to the SEM-EDX if the wafer does not pass the post-scan. Typically transporting of the wafer is done in a protective transport container known in the semiconductor industry as a FOUP (Front Opening Unified Pod) for 300 mm wafers or a SMIF (Standard Mechanical Interface) pod for 200 mm wafers. The cumulative transport time delays identifying and correcting contamination problems in the manufacturing equipment and decreases production time. Other perceived drawbacks to existing wafer scanning tools include complexity (number of parts), large footprint, and high cost.
Accordingly, the need exists for a compact and portable contaminant locating/sizing method and apparatus that overcomes these perceived drawbacks in wafer scanning tools based on the prior art.